Software-Managed Read And Write Wear-Leveling For Non-Volatile Main Memory Part 3

5.1.1 Temporal Write Distribution Sampling.

To generate a trap after every Cwrite sample and write access of the application, we use the CPU internal performance counting mechanism. The BUS_ACCESS_ST event in ARMv8 counts the total number of store requests on the memory bus, and thus the number of write accesses of the application is recorded. For Intel CPUs, the same behavior could be achieved by using a performance counter for writebacks of the last-level cache. 

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If no such performance counter is available in some system, any approximation (e.g., the cycle counter or a timer) still can be considered. The performance counting mechanism allows to generate a trap when the performance counter overflows (i.e., exceeds the value of Cmax = 232 −1). 

To establish traps on every Cwrite sample the write access, the performance counter is set to Cmax −Cwrite sample during the handling of the overflow trap. When choosing the rewrite sample, the introduced overhead for trap handling should be considered.

5.1.2 Write Access Trapping.

As the last written memory address cannot be determined during the trap handling of the performance counter overflow, a second technique is implemented to track the target address of the next memory write. 

During the handling of the overflow trap, the memory access permission for the tracked memory region is set to READ_ONLY. Note that the ARMv8 architecture allows hierarchical memory access permissions, allowing to configure memory regions of 1-GB size to READ_ONLY by only modifying one-page table entry. 

Due to the READ_ONLY permission, the next write access causes a permission violation trap, which is handled as a synchronous interrupt. The violation-causing address is available for the trap handler in a dedicated register, which then is used to increment the corresponding counter in the write distribution approximation.1 

During the handling of the trap, the access permissions are set back to READ_WRITE.2 Note that this mechanism does not strictly require an MMU; it could also be implemented with a very lightweight MPU on a microcontroller. 

However, if an MMU is present, the write access trapping could be limited to a certain subset of memory pages. If, for instance, some timing-critical application relies on fast memory accesses, the write access trapping can be disabled for this application at the cost of bad wear-leveling.

5.2 Read Access Sampling

To record a statistical approximation of read accesses, we follow the same two steps as described before. First, we set up an architectural performance counter that counts read accesses on the memory bus. 

By setting the performance counter value C manually to its maximum value Cmax = 232 − 1 minus a configurable sampling rate Cread sample whenever the counter overflows, an overflow trap is generated for every Cread sample read accesses. 

During the handling of the overflow, we set the memory permissions of all observed memory pages to NO_ACCESS, which leads to a permission violation trap on read and write accesses. This violation trap is utilized to record the target of the next read access. 

During the trap handling, the memory permissions are restored such that the execution can continue. In consequence, this mechanism leads to a sampling of the current read address every Cread sample read accesses. 

In our test system, the read approximation is used alongside the write approximation. Consequently, both methods interfere with each other, since they both use the memory permission system to trap a subsequent memory access. The write approximation only uses the READ_ONLY permission, and therefore read accesses still proceed and the read approximation is not disturbed. 

The read approximation in contrast uses the NO_ACCESS permission, and thus also a subsequent write access causes a permission violation trap, even if currently no sample for the write approximation should be recorded. 

This requires tight cooperation between both approximators to ignore these write traps. However, if the read approximator aims to record a read sample but the next memory access is a write access, the write access has to be completed to continue the execution and reach the read request finally. To complete the write access, the memory permissions have to be relaxed to allow write access again. 

To still trap the next read access, we utilize a debugging mechanism that sets the memory permissions back to NO_ACCESS after the write access is completed. Therefore, we replace the instruction after the write instruction with a breakpoint instruction.3 

As long as write instructions cannot manipulate the program counter,4 the subsequent instruction is guaranteed to be executed. The breakpoint handler then replaces the breakpoint with the original instruction, resets the memory permission to NO_ACCESS, and continues execution.

5.2.1 Instruction Execution Sampling.

When read accesses to main memory are approximated, instruction fetches to the compiled source code should be sampled as well, since they also are memory read accesses. 

However, using the preceding mechanism would lead to only instruction fetches being captured, since the first thing the CPU does after returning from the trap handler that modified the memory permissions is to fetch the next instruction. 

Therefore, only access to the text segment would be captured in the read approximation. To overcome this, we do not observe text section pages for the read approximation and therefore do not modify the permissions for these pages. 

Instead, we take a separate sample of the program counter on every overflow of the performance counter (Cread sample ), which leads to a separate and independent approximation of the text segment.

5.2.2 Approximation Scaling.

As pointed out previously, the read and write approximations are used to estimate the age of memory regions and are fed forward to a coarse-grained wear-leveling algorithm. 

To maintain the quality of the aging-aware wear-leveling algorithm, it is essential to scale the read approximation according to the write approximation. The read approximation may run with a different sample rate Cread sample than the write approximation Cwrite sample for performance reasons. 

The wear-leveling algorithm, however, only gets the estimated cell age as an input, which is the write approximation for a non-read-destructive NVM and the read approximation plus the write approximation for a read-destructive NVM. Thus, the read-and-write approximation must have the same weight. 

The scaled read approximation can be calculated in the following way: the required scaling factor x, which has to be multiplied with the read approximation before it is submitted to the wearleveling algorithm, is calculated according to Equation (1).

X= Cread sample Cwrite sample (1)

5.3 Coarse-Grained Wear-Leveling Algorithm

The access-distribution approximation enables arbitrary aging-aware wear-leveling algorithms. The algorithm does not need to be aware if it is running on a read-destructive NVM or not, because read accesses have the same destructive influences as write accesses. 

Thus, the algorithm can take the age as an input, which is computed from the sum of read and write accesses. We feed the algorithm with an indicator from the access approximation, which estimates the age of each page. Note that the approximation system only operates on virtual memory and does not consider the mapping to physical memory pages. This is maintained by the wear-leveling algorithm itself. 

The wear-leveling algorithm decides which virtual memory pages are relocated to other physical memory pages and therefore maintains the overall age of the physical memory. However, the interface between the approximation system and the wear-leveling algorithm has to be well-defined. We interleave our wear-leveling algorithm further with the approximation implementation to reduce redundantly stored data. 

Our wear-leveling algorithm uses a red-black tree to maintain all managed physical memory pages along with their estimated age [10]. As the estimated age is already present inside of the tree nodes, there is no need to store these values in the approximation implementation as well. 

The tree is illustrated in Section 5.3.1. Each page is stored in the tree about the estimated age, and thus a lookup and extraction of the youngest page is efficiently possible. 

The approximation system maintains a temporary read-and-write counter per virtual memory page and notifies the wear-leveling algorithm with an age increment action if one of these counters exceeds a certain threshold. In consequence, the wear-leveling algorithm increases the internal age value and relocates the physical memory content to another page.

5.3.1 Management of Memory Pages.

Whenever a virtual memory page should be relocated to another physical memory page, the current minimum (i.e., the physical memory page with the lowest assumed age) is extracted from the tree as the target physical page and the estimated ages are adjusted accordingly. 

The choice of the youngest page as a victim of wear-leveling leads to incremental wear-leveling, where every page becomes the youngest page after a certain amount of time. 

Regarding the overhead, the wear-leveling algorithm is only called in this setup when a memory page has to be relocated. Regarding the selection policy of the wear-leveling decisions, the estimated age of all physical pages is balanced equally over time, because every page will be the current minimum page at a certain time. 

This establishes a stateless incremental wear-leveling, and the memory is assumed to be wear-leveled at any time and is kept wear-leveled. Therefore, the system does not need to store ages across power cycles. 

The data structures of the access approximation and the wear-leveling algorithm themselves need to be targeted by wear-leveling itself, which requires a special implementation. 

These technical details, however, are outside the scope of this work. Eventually, this integration of the wear-leveling algorithm and the approximation system leads to an additional configuration parameter, besides the temporal and spatial granularity of the write count approximation, i.e. the threshold relic, after which the number of estimated writes or reads a relocation should be performed. 

This configuration parameter provides a trade-off between the overhead of page relocation and the frequency, and respectively the resulting quality, of wear leveling actions without influencing the quality of the access approximation.

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