Software-Managed Read And Write Wear-Leveling For Non-Volatile Main Memory Part 2

The class of considered systems usually provides many features that are also available in normal desktop computers. For instance, a complete MMU and virtual memory are often used to isolate the address space of several tasks from each other or to restrict hardware access. 

Virtual memory is one of the most important concepts in computer operating systems. It allows computers to use hard disk space as an extended memory so that larger programs can still be executed when memory is insufficient. Virtual memory is closely related to computer memory.

Computer memory is limited. If we do not have a mechanism such as virtual memory, then when memory is insufficient, we can only give up the execution of the program or force some applications to close. The emergence of virtual memory has greatly alleviated this problem. Through the memory space provided by virtual memory, the computer can move the unused parts from the memory to the hard disk according to certain rules. In this way, the computer can expand the memory to be used without increasing the physical memory, allowing us to continue to use more and larger programs.

This mechanism provides us with great convenience. We don't have to care too much about the hardware of our computer. As long as we run the program within the limits of virtual memory, even if our physical memory is very small, our computer can run a variety of different programs, and there is no need to worry about memory overflow and other problems.

It can be said that the expansion of memory in the computer is very necessary. Virtual memory provides us with a better solution. At the same time, it also allows us to make better use of other devices such as hard disks, and fully tap the potential of computers. There is no doubt that the relationship between virtual memory and memory is inseparable. The emergence of virtual memory provides us with the possibility of making greater use of computer hardware without sacrificing computer operating efficiency. It can be seen that we need to improve memory. Cistanche can significantly improve memory because it has antioxidant, anti-inflammatory, and anti-aging effects, which can help reduce oxidation and inflammatory reactions in the brain, thereby protecting the health of the nervous system. In addition, Cistanche can also promote the growth and repair of nerve cells, thereby enhancing the connectivity and function of neural networks. These effects can help improve memory, learning ability, and thinking speed, and can also prevent the occurrence of cognitive dysfunction and neurodegenerative diseases.

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However, this does not imply that a full cache hierarchy is possible and useful. The clock frequency of these systems is usually set to some hundreds of megahertz to reduce power consumption. 

Memory access latencies become less critical under this condition anyway, and a cache would not improve the situation much but would consume further chip area. 

Additionally, to guarantee worst-case execution times, scratchpad memory may be preferred over caches. Therefore, the memory wearout is reduced for the memory regions that are covered by the scratchpad memory, but not for the other regions. 

These remaining regions still need a wear-leveling mechanism. In this article, we focus on the worst case that all memory regions need wear-leveling. Because of the reasons mentioned previously, our target system consists of an embedded processor with full MMU, virtual memory, and no caches. To overcome the disadvantages of single types of memories (e.g., the lifetime of NVMs or the volatility of SRAMs), several systems implement a hybrid memory architecture [7]. 

For these systems, more than one memory type is connected to the CPU (e.g., a FeRAM and an SRAM) and mapped to the CPU address space. The operating system and the application then can actively decide which memory content should be placed in which memory, by storing it in the corresponding address region. 

However, in this work, we only assume one NVM as the main memory in the system and develop our solution for all memory segments allocated to this main memory for two reasons. 

First, if there is a hybrid memory hierarchy with various memories, appropriate maintenance mechanisms for the other memories can be applied separately. We then still provide a wear-leveling mechanism for the NVM part. 

Second, even if a hybrid memory hierarchy is available, the allocation of memory segments may have to obey several constraints, which makes an arbitrary mapping impossible. Hence, memory contents may still have to be allocated to the NVM, which wears it out rapidly. Our solution provides a mechanism to improve the lifetime of a given mapping of memory segments. 

As our proposed methods are software-based, they need to run in an operating system-like layer to have privileged control over the running application. Even if a full operating system may not be present for small embedded systems, a thin software layer is required to manage the hardware, control startup procedures, and manage the control flow. 

Our methods can be implemented in such a basic operating system as well. Although we focus on the described target system class throughout this work, our methods are still applicable to other systems with appropriate modifications. For larger systems with caches, for instance, hits and misses would have to be properly distinguished since the first does not wear out the memory but the latter does.

3.1 Implementation Platform

Since we assess our implemented methods regarding their wear-leveling quality in the evaluation, we use a platform for our implementation where we can precisely extract the age (i.e., the total number of accesses per memory cell). 

We use the full system simulation-based framework from our previous work [10]. This framework runs the gem5 simulator in combination with the NVMain plugin for NVM simulations and a special operating system, which allows a sharp separation of application and operating system memory. NVMain outputs a trace file for each simulation that contains precise information about every memory access (i.e., read and write accesses). 

Later in this work, we describe our implementation of wear-leveling strategies. We implemented these strategies for the bare-metal operating system, running in the simulation framework as well. Therefore, we can directly evaluate our algorithms in a realistic full system simulation and do not rely on any high-level estimate by analyzing the resulting memory access trace from a simulation with enabled wear-leveling. 

We further reuse the benchmark applications [10], since the code is directly available with the simulation framework. Nevertheless, our wear-leveling techniques are independent of the CPU architecture, and the concrete implementation and evaluation are done for an ARM-based 64-bit application processor (ARMv8) due to the memory simulator [10]. 

Note that a concrete implementation on a specific CPU architecture requires several specific implementation details, which are also stated in this article. These details, however, can be reimplemented on other CPU architectures.

4 PROBLEM ANALYSIS

To illustrate the need for wear-leveling and to justify wear-leveling for specific regions, we analyze the memory access behavior of a set of benchmark applications in this section and discuss the influence on memory lifetime. The benchmark applications are presented in detail in the following:

• Dijkstra is part of the MiBench suite [8] and computes the shortest paths in a graph according to the Dijkstra algorithm. The specialty of this benchmark is that the steps of the algorithm are managed in a queue, which is stored in the data segment.

• resolve is part of the NVM simulation setup [10] and solves a system of linear equations according to the Gaussian elimination algorithm. This benchmark directly modifies its input data.

• she is also part of the MiBench suite [8] and computes the SHA-1 hash of given input data.

• qsort is part of the NVM simulation setup [10] and is a recursive implementation of the quicksort algorithm. Therefore, not only is the input data modified, but the stack segment is also used intensively.

• rijndael is part of the MiBench security suite [8] and encrypts given input data with the Rijndael algorithm. For this benchmark, the input is not read from a file but is read from a region in the data segment itself.

• crc32 is also part of the MiBench security suite [8] and computes crc checksums on given input data

Since we target two different scenarios-read-destructive and non-read-destructive NVM systems-we analyze both situations. For non-read-destructive NVM systems, we investigate the total number of write accesses per memory cell, and for read-destructive NVM systems, we investigate the accumulated number of read and write accesses per memory cell. We execute the benchmark applications as described earlier and illustrate the resulting memory access patterns in Figures 1 and 2.

We observe that memory accesses happen at different rates on memory cells of the different memory regions. Generally, despite large regions with uniform access patterns, dense access hot spots can be found. 

These hot spots have a drastic influence on the memory lifetime, because only a few cells wear out intensively, whereas other cells are not used at all. If these accesses were better distributed, the lifetime would be increased drastically. 

For non-read-destructive NVMs (Figure 1), dense write hot spots are mainly found in the stack, which stems from the way stack memory is used. All other regions face fewer write hot spots. For read-destructive NVMs, read hot spots can be also found in the text regions, because the compiled program code resides in this region and is read during execution. 

Overall, we deduce two objectives for our wear-leveling algorithms. First, the regions with different access frequencies have to be detected properly during runtime and have to be relocated to other memory regions, according to the frequency of accesses. We propose a coarse-grained aging-aware wear-leveling algorithm to fulfill this objective. 

Second, the dense access hot spots need to be resolved in such a way that the accesses are spread over a larger region of memory cells. This reduces the stress of single cells and averages the wear-out to a larger region. We propose two fine-grained solutions to achieve this: one for the stack segment and another one for the text segment.

5 COARSE-GRAINED WEAR-LEVELING

In this section, we detail the proposed aging-aware coarse-grained wear-leveling. To assess the age of a memory cell, the memory access behavior has to be tracked. If the current access behavior cannot be tracked by the hardware and no memory trace is known for the running application, aging-aware techniques cannot be applied by default. 

To overcome this issue, we first propose a software-managed access-distribution approximation technique, which estimates the memory access distribution (i.e., the write and read count to fixed-size memory regions) using only commonly available hardware support (i.e., MMU, performance counters, and interrupts). 

This access approximation is implemented as a system service in the runtime environment (e.g., the operating system). The access-distribution approximation can be subsequently provided as an input to an aging-aware wear-leveling algorithm.

5.1 Write Access Sampling

As already introduced, the first step toward software-managed coarse-grained wear-leveling is a proper approximation of the memory access distribution. Although capturing this approximation for write and read accesses is mostly similar, we present the capturing of the write approximation in detail first. Subsequently, we describe the additional steps required to also capture the read approximation. 

Several steps are required to record an approximation of the write distribution of an application at runtime. First, we equally spaced sample every writing sample the write access of the application captured its target address and stored it in an appropriate data structure. 

The number Cwrite sample determines the temporal granularity of the approximation technique, allowing a trade-off between accuracy and introduced overhead. After capturing the write, the spatial granularity of the data structure has to be considered as well. 

Storing the estimated write count for every byte introduces a big storage overhead and leads to imprecise results when the temporal granularity is coarse. Instead, bytes can be related to larger memory blocks and the write counts are aggregated for every write access into these blocks. For our implementation, we aggregate the write counts for 4-kB memory blocks, because the wear-leveling algorithm considers this granularity (i.e., the decision is based on memory pages). 

Using an 8-byte counter for every block, 1 512 · memory-size bytes are required to store the approximated write distribution (e.g., 2 MB when 1 GB of main memory is tracked). 

The detailed flow of capturing the target of every Cwrite sample and memory write access requires two techniques to be implemented. First, a trap has to be generated after every Cwrite sample through the write access, and thus the approximation implementation can take action. Subsequently, the target of a memory write access has to be determined and stored in the data structure. 

Both implementations are stated in detail subsequently. Although the approach by Gogte et al. [6] allows direct capture of CPU write requests at sampled intervals, their approach relies on a specialized debugging capability. 

Our method provides an alternative that makes use of more widely available hardware features. Vogl and Eckert [21] propose to use of performance counters to specifically analyze the instruction execution of an application. We similarly make use of performance counters to analyze the memory usage of an application, in contrast, as described in the following.

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