Software-Managed Read And Write Wear-Leveling For Non-Volatile Main Memory Part 1

In-memory wear-leveling has become an important research field for emerging non-volatile main memories over the past years. Many approaches in the literature perform wear-leveling by making use of special hardware. 

Main memory is a storage device inside a computer. It is used to store temporary data. It can be directly read and written by the CPU and is an indispensable part of the computer system. In contrast, memory is a neuronal structure in the human brain and is an organ responsible for storing and recalling information. Although main memory and memory are physically and functionally different, there are some connections and similarities between them.

First of all, main memory and memory are both important storage devices. Main memory can temporarily store program instructions and data to meet the read and write needs of the CPU. Memory is one of the main organs in the human brain responsible for storing and recalling information, which can help humans perceive and understand the world to a certain extent. Both types of memory have the characteristics of high efficiency, speed, and stability, which can improve the thinking efficiency of computers and humans.

Secondly, both main memory and memory need to be constantly trained and strengthened. Main memory needs to be continuously read and written to ensure the normal operation of the computer system, and it also needs to be optimized and expanded to meet the growing demand. Memory also needs to be constantly stimulated and trained, which can be improved through reading, learning, and exercise. Only by continuous strengthening can main memory and memory better serve computers and humans.

Finally, both main memory and memory need to be properly managed and maintained. Main memory needs to be cleaned and optimized regularly to reduce junk data and improve performance, to avoid problems such as freezing and freezing of computer systems due to excessive junk data. Memory requires frequent recall and organization of information to prevent information from being forgotten and confused. Only in this way can main memory and memory better serve computers and humans.

In summary, although main memory and memory are physically and functionally different, there are also some connections and similarities between them. Through enhanced training, reasonable management, and maintenance, we can better play their roles and promote the development of computer and human intelligence. It can be seen that we need to improve memory, and Cistanche can significantly improve memory because Cistanche is a traditional Chinese medicine with many unique effects, one of which is to improve memory. The efficacy of Cistanche comes from the various active ingredients it contains, including tannic acid, polysaccharides, flavonoid glycosides, etc., which can promote brain health in many ways.

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Since most non-volatile memories only wear out from write accesses, the proposed approaches in the literature also usually try to spread write accesses widely over the entire memory space. 

Some non-volatile memories, however, also wear out from read accesses, because every read causes a consecutive write access. Software-based solutions only operate from the application or kernel level, where read and write accesses are realized with different instructions and semantics. Therefore different mechanisms are required to handle reads and writes on the software level. 

First, we design a method to approximate read and write accesses to the memory to allow aging-aware coarse-grained wear-leveling in the absence of special hardware, providing the age information. 

Second, we provide specific solutions to resolve access hot spots within the compiled program code (text segment) and on the application stack. In our evaluation, we estimate the cell age by counting the total amount of accesses per cell. 

The results show that employing all our methods improves the memory lifetime by up to a factor of 955×.

CCS Concepts: • Computer systems organization → Embedded systems; • Hardware → Memory and dense storage.

Additional Key Words and Phrases: Non-volatile memory, wear-leveling, read-destructive, age approximation.

1 INTRODUCTION

In recent years, non-volatile memory (NVM) has been considered as an alternative to DRAM or SRAM for memory. Due to several drawbacks (e.g., a lower cell endurance), maintenance strategies have been proposed in the literature to overcome the impacts. 

Memory lifetime is a crucial issue when NVMs are considered because they can shrink to hours or even minutes when no maintenance is applied [5, 9]. Therefore, wear-leveling strategies try to extend the memory lifetime to the maximum by stressing all memory cells equally over time. 

Wear-leveling strategies can be categorized as aging-aware and non-aging-aware strategies, where aging-aware strategies investigate the current cell ages to make adequate wear-leveling decisions. 

This requires precise knowledge about the cell ages, which can be either gathered from special hardware or can be approximated by software. Non-aging-aware strategies, in contrast, base their wear-leveling decisions on other mechanisms (e.g., on random). Most aging-aware and non-aging-aware strategies usually only target write accesses, because only write accesses wear out the memory cells for most NVM types. Some NVMs, such as Ferroelectric RAM (FeRAM), are also read-destructive [18]. 

This means that every read access also wears out the memory cell. For FeRAM, the reason is that read accesses overwrite the current cell value and thus it has to be recharged subsequently [18]. Therefore, every read access results in an automatic subsequent write access to the cell. The memory controller triggers this process during every read access. 

Consequently, read accesses have to be considered with the same impact as write accesses during wear-leveling if such read-destructive memories are used. Although this does not imply a significant difference on the hardware level (especially hardware-based wear-leveling), because hardware can simply be extended to track read accesses as part of the wear-leveling, it does so on the software level. If wear-leveling is realized in software, tracking and counting read accesses differs from write accesses. 

Read and write accesses happen with different semantics on the software level, and indeed there are various "read-only" data in most programs. Thus, the different semantics have to be considered during the design of software-based solutions. 

In this article, we study the design of software-managed wear-leveling, where we investigate the design and usage of age approximations for aging-aware wear-leveling in the absence of special hardware. By our software-managed mechanism, we hereby denote a solution that is not fully independent of the underlying hardware and still requires a certain set of system features. 

We rather consider solutions, which configure commonly available hardware components from the software level and therefore can be implemented purely on the software level of state-of-the-art systems. More specifically, our solution requires an MMU and performance counters, which can be found in many recent application processors. 

The solution, however, does not propose a modification of the aforementioned hardware but only manages and configures it from the software level to achieve the wear-leveling goals. 

A software-based solution in general must not be favorable over a hardware-based solution but rather offers a wear-leveling solution for systems where the required hardware support is not implemented, either on purpose to save chip space or because the system hardware is already configured. 

We further cover the destructive influence of read and write accesses within our method, such that read-destructive NVMs can also be targeted. First, we design coarse-grained aging-aware wear-leveling, where we sample read and write accesses to the main memory with the help of performance counters and memory access permissions. 

This provides us with a statistical approximation of the read-and-write access distribution. We feed this approximation into a virtual memory page-based wear-leveling algorithm, which remaps the physical memory pages behind the virtual memory pages in an aging-aware manner. 

As an orthogonal, we further design non-aging-aware fine-grained wear-leveling, which resolves dense access hot spots within memory pages. The application stack segment faces intensive hot spots of dense read and write accesses, whereas compiled program code (i.e., in the text segment) only faces read hot spots. 

Targeting this, we propose a mechanism that moves the stack and the text segment circularly with small offsets through the physical memory while the correct execution of the program is ensured. In combination with the preceding coarse-grained aging-aware wear-leveling, we achieve allover wear-leveled memory, even in the presence of a read-destructive main memory.

Our novel contributions include the following:

• An online read-and-write approximation to allow coarse-grained page swapping concerning read-and-write accesses.

• A fine-grained wear-leveling for the stack segment to avoid write and read hot spots. The stack is moved rotationally while the correctness of pointers is maintained.

• A fine-grained wear-leveling for the text segment to avoid read hot spots. This approach rotationally moves the text segment to spread read hot spots through a larger memory area.

2 RELATED WORK

Over the past decades, several approaches for in-memory wear-leveling for NVM have been proposed. These approaches can be categorized along different criteria. 

First, there are aging-aware approaches [1, 2, 4–6, 11, 15, 17, 20, 24], which take the current cell age into account to apply wear-leveling. In contrast, randomized approaches [5, 19, 24] apply wear-leveling in a circular or randomized manner. 

Both approaches are often combined to achieve a randomized wear-leveling on fine granularities inside of memory blocks, whereas an aging-aware approach is used to target these coarse-grained memory blocks. 

The granularity also varies from single bits [3, 23] over cache lines [19, 24] for fine-grained approaches to memory pages [1, 2, 5, 6, 20] or even bigger memory segments [22, 24] for coarse-grained approaches. Some approaches are not based on remapping the physical memory content through an abstraction layer but hook into the memory allocation process of the operating system to apply wear-leveling to the memory allocator [1, 15, 20]. 

Li et al. [15] also propose to use an allocated memory portion, whenever a function is called, for the function's stack memory to wear-level the stack region.

2.1 Aging-Aware Wear-Leveling

Gogte et al. [6] propose a software-only coarse-grained wear-leveling approach by using a sampled approximation of the write distribution. They make use of advanced debugging capabilities, such as Intel Processor Event-Based Sampling (PEBS), which allows them to sample the write requests from the CPU. These debugging capabilities, however, can rarely be found in embedded systems and resource-constrained hardware. 

All other mentioned aging-aware approaches rely on the current write-count information of the memory. Most approaches introduce specialized hardware into the memory controller to collect the write-count information, which is not available in commonly available systems and might be hard to realize. 

Dong et al. [4] use an offline recorded memory trace to estimate the write distribution, which limits the approach to a subset of well-known applications only.

2.2 Read Wear-Leveling

To the best of our knowledge, there are no dedicated algorithms for read wear-leveling in readdestructive NVMs. However, hardware-based approaches that are not aging-aware or that directly decide based on the wear of each cell are compatible with read-destructive memories by default. 

If the wear is estimated from the write count, it could be also estimated from the read and write count together. This implies that hardware-software interplay algorithms can obtain accurate wear estimation by extending the hardware to count read accesses. 

As long as generic mechanisms (e.g., virtual memory page remapping) are used [1, 2], the modifications to the algorithms are minimal. In contrast, when specific mechanisms (e.g., heap allocation or stack allocation) are used for wear-leveling [14, 15, 20], then read wear-leveling cannot be integrated easily. Thus, another special mechanism for read wear-leveling is required in those cases. 

In addition, for algorithms that ship with their write approximation [6, 9, 12], a specialized read approximation has to be added. To the best of our knowledge, this is the first work to propose a software-managed memory read-and-write access approximation that does not rely on special debug capabilities. 

Furthermore, specific algorithms are provided, which operate on application-specific data (stack and text), where the algorithm for text is dedicated to read accesses only.

3 TARGET SYSTEM

In this section, we first scope the typical target setup of our proposed methods. Although we do not limit our methods to specific NVM types, we consider certain properties regarding the wear-out. We assume any cell modification wears out a cell equally. 

We further do not assume iterative writing, and thus the number of memory accesses corresponds to the memory lifetime linearly. In our proposed method, we target write-destructive, as well as read-destructive, NVMs by implementing an add-on for read-destructive NVMs. 

Although the read-destructive property may not only be found in one NVM type, FeRAM is a prominent example of such an NVM. This, however, does not imply that our method is limited to FeRAM; it could be also applied on a non-read-destructive NVM, for instance, by not enabling the read-wear leveling. 

The read-destructive property of FeRAM stems from the fact that the reading procedure (i.e., the sensing of a cell value) overwrites the cell [13, 18]. During the read operation, an electric field is applied to the FeRAM cell, and the transferred charges are measured, which polarizes the cell. To maintain the original cell state after reading, the old value has to be written to the cell again. 

This necessary subsequent write access makes FeRAM read-destructive. As the target system, we consider embedded systems in resource-constrained environments, which have to fulfill complex tasks and therefore also run complex software. 

This kind of system can be found in automotive controllers or aerospace applications. Equipping them with NVM is desirable to increase the memory capacity at low costs while maintaining a low energy consumption. In the following, we scope our target system concerning (1) the cache hierarchy and (2) the general memory architecture.

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